FPGA Design Engineer IND

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

We are actively seeking an FPGA Design Engineer based in Hyderabad, India.

Responsibility:

• Will be a key member of a small FPGA team that will own prototyping of Kandou’s architectures in FPGA

• Will need to work independently with low day-to-day supervision and own FPGA projects

• Will work with Kandou’s architecture and system software teams on FPGA prototyping and participate in the entire lifecycle of project including support.

• Will participate in technical discussions with IP providers and be responsible for driving some of them.

‪Skills:

• Demonstrated RTL development skills of 5+ years, only 1 can be academic

• Proficiency in Verilog and C programming is expected. Proficiency in using Linux for lab testing is expected.

• Working exposure for SystemC and scripting (Python) is desired.

• Clear understanding and usage of AXI and related AMBA protocols to connect multiple logical blocks in an FPGA

• Demonstrated computer architecture understanding in at least one of processors, PCIe , ethernet or storage protocols

‪Preferred Experience:

• Must have shipping FPGA design in at least one of the following: compute accelerators, networking, storage, processor prototyping

• Must have micro-architected, designed & shipped at least two key logic functions of high or medium complexity in an FPGA design

• Must have participated in lab bring up & validation of shipping FPGAs in the lab and in deployed use

• Must be familiar with Xilinx development tool chain and Versal, Virtex FPGAs

• Preferred: Deep exposure to PCIe devices – protocol design & lab work

• Preferred: Deep exposure to data path blocks (PCIe, Networking or storage) that involved embedded processors in the FPGA.

Education

• 4 year Bachelor of Tech/Engineering/equivalent in Computer Science, Computer Engineering, Electronics or related field

• Master of Tech/Engineering/equivalent in Computer Science, Computer Engineering, Electronics or related field is a plus but not required.

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/